‍H5TQ4G83AFR-PBC产品信息：

品牌：SK hynix/海力士

型号：H5TQ4G83AFR-PBC

容量：4GBIT

技术： DDR3 SDRAM

描述：H5TQ4G83AFR-PBC IC FLASH DRAM 4Gbit 96-FBGA

产品族：存储器

格式：闪存

H5TQ4G83AFR：
The H5TQ4G43AFR-xxC, H5TQ4G83AFR-xxC and H5TQ4G63AFR-xxC are a 4Gb CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Features：
 VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
Programmable burst length 4/8 with both nibble equential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle   (Tcase of 0oC~95oC) 
- 7.8 µs at 0oC ~ 85 oC                                                               
- 3.9 µs at 85oC ~ 95 oC
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
This product in compliance with the RoHS directive.
描述：H5TQ4G83AFR-PBC IC FLASH SDRAM 存储器 4Gbit 96-FBGA